Design and Performance Analysis of Low Power High Speed Adder and Multiplier Using MTCMOS in 90nm, 70nm, 25nm and 18nm Regime

نویسندگان

چکیده

Nowadays, VLSI technology mainly focused on High-Speed Propagation and Low Power Consumption. Addition is an important arithmetic operation which plays a major role in digital application. Adder act as the applications of signal processing, memory access address generation Arithmetic Logic Unit. When number transistors increases system designs, makes to increase power complexity circuit. One dominant factors reduction low overcome dissipation existing adder circuit, MTCMOS technique used proposed adder. The design simulated 90nm, 70nm, 25nm 18nm then comparison made between context energy, area delay. In this comparison, efficiency metrics delay are found be reduced 20% from for multiplier.

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ژورنال

عنوان ژورنال: Advances in parallel computing

سال: 2021

ISSN: ['1879-808X', '0927-5452']

DOI: https://doi.org/10.3233/apc210075